A bipolar transistor of the vertical type is known for example from EPA-0 632 505, and is described hereinafter with reference to FIG. 1. In detail, on a substrate 1 of monocrystalline silicon of N type, there is grown a first epitaxial layer 2, also of N type, but with a lower concentration of doping agent than the substrate 1. On the surface of the first epitaxial layer 2 there is formed, by means of ion implantation and subsequent diffusion steps, a base buried region 3, of P type, and on the latter, an emitter buried region 4, of N type, of which the portion which forms an emitter finger of the interdigitized structure can be seen in full in the FIG. 1. A second epitaxial layer 9 of N type is grown on the first epitaxial layer 2 Then, inside the second epitaxial layer 9, there is formed by ion implantation and a subsequent diffusion step, a sinker or deep base region 6, of P type, with a comb shape, the fingers of which surround the emitter fingers and reach the base buried region 3, forming the surface contacts of the transistor base region.
Subsequently, through the second epitaxial layer 9 there are provided sinker emitter regions 5 and 5a, which are respectively peripheral and central, of N type, which reach the emitter buried region 4, and form the surface contacts of the emitter region of the transistor, with predetermined dimensions and resistivity, such as to form balancing resistors. In particular, the sinker peripheral regions of the emitter 5 extend onto the outer perimeter of the emitter fingers, whereas the sinker central regions of the emitter 5a extend to the centre of the fingers.
Subsequently, screen regions 7, of P type, are provided in the second epitaxial layer 9, inside regions delimited by the sinker peripheral emitter regions 5 and outside the sinker central emitter regions 5a. A comb-shaped surface region 8, of N type, is then provided, the fingers of which extend inside the screen region 7, such as to provide simultaneously a connection between the emitter regions 4 and 5a and the surface of the silicon chip, and distributed balancing resistors (ballast resistors) for the emitter. Therefore, the screen region 7 isolates electrically the fingers formed by the sinker emitter region 4 from the surface region 8, with the exception of the central portion of the fingers.
Then, using known metallization and passivation techniques, on the front surface of the chip the electrodes of the base 10, of the emitter 11, and a metallization line 12 for biasing of the screen region 7 are provided, and on the rear of the chip the collector electrode 13 is provided.
This structure solves the problem of emitter currents which flow through the second epitaxial layer 9 delimited by the sinker peripheral emitter regions 5, which reduce the safe operating area (SOA); however the structure described involves the existence of parasitic components (SCRs and transistors in series with the power transistor) which can be activated in specific conditions, jeopardizing the performance of the power transistor, and a photo lithographic step is required for forming the screen layer 7, and an increased size owing to the presence of the metallization line 12.